`include "define.v"
module DATAMEM(
    input wire clk,
    input wire ce,
    input wire we,
    input wire [31:0] addr,
    input wire [31:0] dataIn,
    output reg [31:0] dataOut
);
integer i;
reg [31:0] datamem [1023:0];
initial begin
    for(i=0;i<1024;i=i+1)
    begin
        datamem[i]=i;
    end
end
always @(*)
    if(ce==`Disenable)
        dataOut = `Zero;
    else
        dataOut = datamem[addr[9:0]];

always @(posedge clk) 
    if(ce==`Enable && we==`Enable)
        datamem[addr[9:0]] = dataIn;
//    else
//        datamem[addr[11:2]] = `Zero;
endmodule


